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CERN-wide meetings, trainings and events
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Ultimi arrivi:
2024-09-04
14:23
How to treat brain tumours with radioactive isotopes - the application of 225Ac in targeted alpha therapy
/
Merlo, Adrian
(speaker)
2024 - 5036.
Training Events; How to treat brain tumours with radioactive isotopes - the application of 225Ac in targeted alpha therapy
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How to treat brain tumours with radioactive isotopes - the application of 225Ac in targeted alpha therapy
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2024-08-12
16:52
Physics requirements on Vertex detector performance
/
Azzi, Patrizia
(speaker) (INFN Padova (IT))
2024 - 2828.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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MAPS detectors technologies for the FCC-ee vertex detector
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2024-08-06
15:56
Discussion
2024 - 407.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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MAPS detectors technologies for the FCC-ee vertex detector
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2024-08-05
13:55
Discussion
2024 - 1949.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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MAPS detectors technologies for the FCC-ee vertex detector
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2024-08-05
13:55
Discussion
2024 - 1833.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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2024-07-16
15:13
Panel 3: Intelligent computing systems
/
Botta, Cristina
(speaker) (CERN) ;
Lintermann, Andreas
(speaker) (Jülich Supercomputing Centre, Forschungszentrum Jülich GmbH)
2024 - 2357.
CERN70 Public Events at CERN; Exploring farther: machines for new knowledge
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Exploring farther: machines for new knowledge
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2024-07-10
10:35
LoCod: an open-source hardware/software co-design tool for SoC/FPGA
/
Manni, Florent
(speaker) (CNES)
LoCod (French acronym for “codesign software”) is an open-source hardware/software codesign tool, targeting Zynq UltraScale+ and NanoXplore NG-Ultra systems-on-chip and could be extended to any heterogenous target including FPGA and processor. From a C language source code, developers can choose, with basic code decoration, which functions of the algorithms should be implemented on the FPGA and which are to run on the CPU. LoCod then automatically performs the code conversion and hardware implementation, as well as the interfaces to transmit data between CPU functions and FPGA functions.
[...]
2024 - 1421.
FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting
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1st FPGA Developers' Forum (FDF) meeting
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2024-07-10
08:46
From C to Routed Circuits for FPGAs in Seconds
/
Guerrieri, Andrea
(speaker) (HES-SO and EPFL) ;
Guerrieri, Andrea
(speaker)
Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation.
[...]
2024 - 1568.
FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting
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1st FPGA Developers' Forum (FDF) meeting
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2024-07-09
16:43
Welcome and introduction
/
Palla, Fabrizio
(speaker) (Universita & INFN Pisa (IT))
2024 - 472.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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MAPS detectors technologies for the FCC-ee vertex detector
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2024-07-09
16:31
MAPS sensor developments in ALICE
/
Reidt, Felix
(speaker) (CERN)
2024 - 2077.
Workshops; MAPS detectors technologies for the FCC-ee vertex detector
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MAPS detectors technologies for the FCC-ee vertex detector
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